In case a defect in semiconductor process technology, severing and short circuits may occur to bit lines of a non-volatile memory device during a manufacturing process. For instance, due to the ever-decreasing dimensions of non-volatile memory devices, adjacent bit lines are becoming closer to each other. As a result, it is likely that during a manufacturing process a short circuit occurs because a bit line contact window is overly close to an adjacent bit line.
Hence, it is necessary to perform a testing process on a non-volatile memory device during a manufacturing process thereof not only to ensure that charges are appropriately injected into a memory cell by a programmed operation performed thereon, but also to determine whether the non-volatile memory device is defective. To this end, the prior art requires that the testing process work in conjunction with a computation process for configuring the address of a defective memory cell in order to enable subsequent configuration of a redundant memory cell. The computation process is disadvantageously time-consuming.